The present invention relates generally to communication networks, and more specifically, to a SONET data byte switch.
Network switches are used to switch network traffic at high speeds between ports and enable information (formatted in packets) to be switched from one port to another based upon addresses embedded in the packets. Packet switching decisions are performed by processors incorporated within each switching node. A local static random access memory (SRAM) for temporarily storing ingress and egress packets is incorporated within each of the switch nodes.
An example of a conventional SONET/SDH STS-1/STM-1 SRAM based digital cross connect is shown in FIG. 1. The system includes a plurality of input ports and output ports and is configured such that data entering each input port can randomly cross switch to any of the output ports. The system utilizes two SRAM memory banks that are each 128 bytes wide and 48 words deep for each output port. The memory banks use a “ping-pong” design. In the example shown in FIG. 1, there are 256 instances of these memory banks across the 128 ports. Each SRAM is designed to accommodate one byte wide timeslot from each of the 48 STS-1s in every input STS-48 signal. While one memory bank (bank 1) is being written input frame data in order from all ports, the other memory bank (bank 2) is being read out randomly from previous stored frame data. For example, for STS-48, every 48 clocks bank 1 is sequentially written with one byte from each STS-1 in each STS-48, while 48 words are read in random order from bank 2. In the next cycle of 48 clocks, bank 1 is randomly read and bank 2 is sequentially written. This process continues alternating between read and write of the two banks at 48 clock intervals.
As can be observed from the foregoing, this conventional design structure requires a large amount of SRAM when supporting 128 or even more ports in an ASIC (application-specific integrated circuit) design. Conventional SRAM based cross connect designs, such as the one described above, are becoming increasingly dense, thus increasing costs and preventing ASIC expansion for future designs.
There is, therefore, a need for a data byte switch that reduces the amount of SRAM required without losing currently available functionality.